Linked Questions
20 questions linked to/from Define make variable at rule execution time
3
votes
2
answers
19k
views
makefile use variable defined in target [duplicate]
How can one use the variable defined inside a make target
.PHONY: foo
VAR_GLOBAL=$(shell cat /tmp/global)
foo:
echo "local" > /tmp/local
VAR_LOCAL=$(shell cat /tmp/local)
echo ${...
- 632
386
votes
17
answers
642k
views
How to print out a variable in makefile
In my makefile, I have a variable 'NDK_PROJECT_PATH', my question is how can I print it out when it compiles?
I read Make file echo displaying "$PATH" string and I tried:
@echo $(...
- 111k
290
votes
7
answers
224k
views
How can I use Bash syntax in Makefile targets?
I often find Bash syntax very helpful, e.g. process substitution like in diff <(sort file1) <(sort file2).
Is it possible to use such Bash commands in a Makefile? I'm thinking of something like ...
- 66.3k
191
votes
6
answers
230k
views
Multi-line bash commands in makefile
Considering that every command is run in its own shell, what is the best way to run a multi-line bash command in a makefile? For example, like this:
for i in `find`
do
all="$all $i"
done
...
- 8,093
68
votes
6
answers
98k
views
Change Makefile variable value inside the target body
Is there a way to reassign Makefile variable value inside of the target body?
What I am trying to do is to add some extra flags for debug compilation:
%.erl: %.beam
$(ERLC) $(ERLFLAGS) -o ebin $...
- 683
45
votes
3
answers
31k
views
Can't assign variable inside recipe
How do I make this work? It errors out with "make: somevariable: Command not found"
sometarget:
somevariable = somevalue
Full example:
CXXFLAGS = -I/usr/include/test -shared -fPIC
OBJ = main.o ...
- 13.7k
28
votes
2
answers
33k
views
Makefile assign command output to variable
I have a script that compresses my css files and outputs the filename of the output file.
I'm trying to build a makefile to automatize the process:
all:
@echo "Compiling CSS"
CSS_OUTPUT=$(...
- 8,098
11
votes
3
answers
5k
views
reevaluate makefile variables
Is there a way to reevaluate a variable's definition upon each use? For example:
MAP_FILES = $(shell find $(TMP) -name "*.map")
all: generate_map_files work_with_map_files
generate_map_files:
./...
bob
1
vote
4
answers
6k
views
AWS Cloudformation | How to Configure Lambda to Use Latest Code in S3 Bucket
Tests3bucketLambda:
Type: "AWS::Lambda::Function"
Properties:
Code:
S3Bucket: TestS3Bucket
S3Key: Tests3.zip
FunctionName: "test-lambda-function"
...
- 111
1
vote
1
answer
7k
views
How to define a global variable in makefile
I declared a variable in the make file like this-
var_COVERAGE_FLAGS?=
I assigned a value to the variable in a target called coverage
coverage:var_COVERAGE_FLAGS = -MDevel::Cover=-silent,on,+...
0
votes
1
answer
812
views
Pass variable to child make only if defined
I can pass a variable to child make using make -C VAR=$(VAR) target (preferring this to export because the variable is only meaningful for a single target). However, it appears that if VAR variable ...
- 171k
0
votes
1
answer
1k
views
Make return error 127
Am trying to match specific string after doing subst on a variable ; substitution is ok but while trying to match make returns error 127.
Does anyone know what's going on here ? why make should ...
- 3
1
vote
2
answers
553
views
GNU Make | Can target and prerequisites of rule be changed at execution time?
I am using target-specific variable values in make, they are OK but it's not applied in targets and prerequisites, just in recipes. Here is the Makefile:
CXX := g++
TARGET := exec
BIN.PATH =
SOURCES ...
- 539
1
vote
2
answers
524
views
Is it possible to suppress variable inheritance for a specific prerequisite?
I have a C++ project that produces a shared library and I want to add tests to it, in a separate executable that dynamically links with the library. So the relevant part of the Makefile looks like ...
- 479
1
vote
1
answer
461
views
Is a target-specific variable the proper tool to conditionally set a variable?
I'm working on the issue described below. When researching it, the GNU Make manual, Section 6.11, says:
Variable values in make are usually global; that is, they are the same
regardless of where ...
- 103k