All Questions
Tagged with volatile memory-barriers
75 questions
1
vote
1
answer
67
views
About StoreLoad Memory Barrier
I don't understand StoreLoad.
Does store1 StoreLoad load2 mean that the CPU's store instruction cannot be reordered after StoreLoad and the load instruction cannot be reordered before StoreLoad?
If ...
5
votes
1
answer
297
views
Deeply understanding Volatile and Memory Barriers
I have been reading a ton on this topic over the past view days but would really like clarification on what I learned so far in relations to C# and C. Firstly, Atomicity seems to be fairly intrinsic ...
4
votes
0
answers
206
views
How CPUs Use the LOCK Prefix to Implement Cache Locking and ensure memory consistency
In Java, adding the volatile keyword to a variable guarantees memory consistency (or visibility).
On the x86 platform, the Hotspot virtual machine implements volatile variable memory consistency by ...
0
votes
1
answer
167
views
arm gcc: store-store ordering without volatile?
I am trying to use a shared index to indicate that data has been written to a shared circular buffer. Is there an efficient way to do this on ARM (arm gcc 9.3.1 for cortex M4 with -O3) without using ...
3
votes
1
answer
153
views
Visibility of volatile writes in C#
According to section 14.5.4 of the C# language spec (ECMA 334, 6th Edition), volatile fields are all about preventing reordering:
14.5.4 Volatile fields
When a field_declaration includes a volatile ...
0
votes
0
answers
43
views
Why are the output of these two java programs different
import java.util.concurrent.TimeUnit;
public class VolatileDemo1 {
private static Object stop;
public static void main(String[] args) throws InterruptedException {
Thread t = new ...
0
votes
2
answers
98
views
Does a volatile write/read ensure visibility of "nearby" fields?
Just a simple example. No need to explain lock, Interlocked and so on.
The bool signals whether a value for state is available. state and the bool is not further modified afterwards.
int state;
...
3
votes
3
answers
358
views
Why does memory-barrier prohibit optimization on static global variable?
The following code contains an interrupt-service-routine and a normal function func(), which uses the global flag and additionally the static global g. Without any memory-barrier this code is faulty, ...
0
votes
0
answers
142
views
General memory-barrier versus special volatile access (on AVR)
In the follwing code I provide three versions of the function getSeconds().
Version 1 uses a simple cli-assembler instruction (volatile) and volatile restore of SREG and a volatile access of the ...
4
votes
2
answers
339
views
Java volatile memory ordering and its compilation on x86-64
Consider the following simple Java application:
public class Main {
public int a;
public volatile int b;
public void thread1(){
int b;
a = 1;
b = this.b;
}
...
1
vote
4
answers
985
views
How compiler enforces C++ volatile in ARM assembly
According to cppreference, store of one volatile qualified cannot be reordered wrt to another volatile qualified variable. In other words, in the below example, when y becomes 20, it is guaranteed ...
1
vote
2
answers
1k
views
C - volatile and memory barriers in lockless shared memory access?
Hi I had a general question regarding usage of volatile and memory barriers in C while making memory changes in shared memory being concurrently accessed by multiple threads without locks.
As I ...
5
votes
1
answer
101
views
Is it safe to assume volatile semantics when reassigning a struct field with a volatile field inside?
Take a look at the example below:
struct MyStruct
{
private volatile int _field;
public void Set(int v) => _field = v;
}
class MyClass
{
private MyStruct _myStruct;
// is it same ...
2
votes
4
answers
382
views
Is this understanding correct for these code about java volatile and reordering?
According to this reorder rules
reorder Rules
if I have code like this
volatile int a = 0;
boolean b = false;
foo1(){ a= 10; b = true;}
foo2(){if(b) {assert a==10;}}
Make Thread A to run foo1 and ...
4
votes
0
answers
505
views
What are cases where the MSVC c++ compiler option /volatile:ms and /volatile:iso show differences in the output assembler?
The following msvc command line option suggests that memory fences are introduced using the option /volatile:ms (default) but not when using /volatile:iso. I have not been able to come up with any ...