2,820 questions
0
votes
0
answers
25
views
DMA Channel Not Starting in PYNQ when Transferring Data with Custom IP [closed]
I am working on a project with PYNQ, where I have designed a custom IP for matrix multiplication in Vivado. I am using AXI DMA for data transfer between the FPGA and the host. I have encountered an ...
2
votes
1
answer
53
views
Verilog full adder
This is the Verilog question. I have written the code according to the image, but I'm getting mismatch in the output, can I get some assistance?
module add1 ( input a, input b, input cin, output ...
- 61
0
votes
0
answers
32
views
Creating a 2 single ended clocks from a differential on board clock on xc7k160tfbg676 FPGA module [closed]
I'm using this FPGA module - https://wiki.trenz-electronic.de/display/PD/TE0741+Resources which has on module HW differential clock named 'sys_diff_clock'. This clock is using the 'Clocking wizard' ...
- 11
0
votes
1
answer
38
views
For some reason, when allocating memory from user space linux, I have a problem with the write response in AXE Memory Mapped to PCI Express module
I have a PC as a root complex and Xilinx fpga device as an end point that writes via PCI Express to root complex RAM using DMA and a linux driver to it. I have a problem that I can't solve in any way. ...
- 1
0
votes
0
answers
20
views
m_axis_result_tvalid is not asserting during floating point operation
I'm trying to do some operations in a Xilinx FPGA. Here is my code. When i simulate the code, the error validation signal does not assert. i need the signal to allow the next step of operations to ...
- 11
0
votes
1
answer
61
views
Vivado 2024.1 – Warning: [Synth 8-7080] Parallel synthesis criteria is not met – what does it mean and how to resolve it?
I'm using Vivado 2024.1 with full-project synthesis (not out-of-context), and I’m getting this warning during synthesis:
[Synth 8-7080] Parallel synthesis criteria is not met
The design builds and ...
- 6,685
-1
votes
0
answers
57
views
VHDL A Fatal Runtime Error was detected. Simulation Cannot Continue During PID Behavioral Simulation
I'm an FPGA Beginner. I'm trying to implement a PID controller on an FPGA chip.
I'm running into problems, particularly during implementation. For simplicity's sake, I only added a proportional ...
- 11
-1
votes
0
answers
67
views
LCD doesn't display text (Verilog)
I'm trying to display "0123456789ABCDEF" on a 16X02 LCD, using Basys3 (100MHZ clock frequency, 3.3V pmod).
Unfortunately, The screen only lights up in a bright green color.
According to the ...
3
votes
2
answers
49
views
ATF16V8, is it possible to use OE value
Good day to everyone.
I suppose the answer to my question will be no, but maybe I misunderstood something.
I need to make an 8-bit flip-flop, with a preset (constant) on the RESET signal.
It would ...
- 63
2
votes
0
answers
53
views
Shared memory between RISCV vm (using Qemu) and host
I can't set correctly shared memory for Qemu RISCV emulation.
My intention is to create a portion of shared memory between Qemu RISCV emulator and the host server. I need this because my intention ...
- 21
2
votes
1
answer
80
views
Is it okay to use level-triggered registers on an FPGA? [closed]
I'm trying to make a single-cycle processor and I was planning on doing something like the following:
Clock rising edge: Opcode is latched onto output of block memory (this must be on a rising edge), ...
1
vote
1
answer
67
views
Winsocket UDP : works only when wireshark launched
I have FPGA device which is waiting for UDP packet "FFFF" on port 1000, then answers also with UDP "FFFF".
This code works fine, I see incoming "FFFF" packets on my JTAG, ...
- 15
2
votes
1
answer
54
views
Is it possible to add external SRAM on a FPGA card
When considering deploying a deep learning model on an FPGA acceleration card (such as an AMD Alveo U50), the onboard SRAM may be insufficient, and its bandwidth is significantly higher than that of ...
- 133
0
votes
0
answers
47
views
srsUE on FPGA not connecting to srsRAN
I'm running srsUE on FPGA, buildroot with 2 CPUs and 1G memory. srsRAN is running on my laptop, ubuntu 22. I use dockerized version of 5gc.
srsUE and srsRAN connected through ZMQ and on a local ...
- 25
0
votes
1
answer
77
views
What's the difference between a constant and an inline constant in Vivado?
I'm currently working on a simple project on an FPGA and wanted to set an enable-input to 1. Now when using the built in IPs for a constant, two components show up. One is "Constant" and the ...
- 13