xilinx
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Mar 22, 2020 - SystemVerilog
The Sphinx documentation flow was extended by several sphinx and third party extensions. These extensions should be documented along with their modifications. A comprehensive syntax guide should be assembled, to collect all syntax notations at one place instead of dozens of third party documentation websites with partially poor usage descriptions.
Extensions list:
- Standard Sphinx extensi
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Jul 9, 2019 - C++
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Feb 12, 2020 - C
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May 17, 2020 - C
Here is a simple example for Vivado.
def vivado_resources(self):
report_path = self.out_dir + "/" + self.project_name + ".runs/impl_1/top_utilization_placed.rpt"
with open(report_path, 'r') as fp:
report_data = fp.read()
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May 22, 2020 - Verilog
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Nov 25, 2019 - SystemVerilog
I have a couple contributions to make to the documentation found at http://www.rapidwright.io/docs/. Is there place to submit these contributions?
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Jan 5, 2019 - VHDL
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Jul 2, 2020 - Verilog
Vendor tools dram tests were not enabled until #1234 got merged.
With SymbiFlow/symbiflow-arch-defs#1268 I have temporarily disabled the vivado_targets, to let CI go green (as it has been red for too long now).
This issue is to keep track of the problem with DRAM evaluated on vendor tools with fasm2bels.
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May 26, 2020 - C++
Add command line option, to enable the user to choose which builder he/she wants to use. Suggestion:
--builder BUILDER specify the builded to be used
By adding it, it would allow:
- Users to actively choose the builder the way to use, without any code change (e.g. editing
hdl_checker/builder_utils.py
). - to separate use cases and make it easier to track bugs that may arise.
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Sep 18, 2017 - C
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Oct 28, 2019 - Python
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Apr 18, 2020 - Verilog
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557 bits isn't too many. Most of these are likely related to the DSP, as 1 DSP is being used: