adibis / DDR2_Controller

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DDR2 memory controller written in Verilog

Updated Feb 28, 2012
Verilog

Gowtham1729 / Image-Processing

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Image Processing Toolbox in Verilog using Basys3 FPGA

python fpga ram pixel vhdl python3 verilog brightness convolution motion-blur verilog-hdl basys3 hsync basys basys-board coe verilog-project basys3-fpga

Updated Jan 9, 2020
VHDL

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

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Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Oct 31, 2018
Verilog

neelkshah / MIPS-Processor

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5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor stage computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

pobu-arch / pumpkin

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computer-architecture cpu-model microarchitecture verilog-project

Updated Jul 22, 2019
Verilog

LutingWang / FPGA

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BUAA Computer Organization Project8 FPGA

fpga computer-architecture mips32cpu verilog-project

Updated Jan 19, 2019
Verilog

vedic-partap / Computer-Organization-and-Architecture-LAB

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Solution to COA LAB Assgn, IIT Kharagpur

cpu mips-assembly verilog hardware-designs coa verilog-project

Updated Jan 10, 2019
Verilog

MaorAssayag / Computer-Engineering-Projects

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Digital computer structure, Hardware Design Lab & Introduction to Computers for computer engineering projects in C, C#, Assembly, Pspice.

c visual-studio csharp communication application-design controller assembly verilog autonomous-vehicles comunication codewarrior pspice systemverilog-simulation verilog-project

Updated Jan 19, 2019
Verilog

mongrelgem / Verilog-Adders

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Implementing Different Adder Structures in Verilog

verilog hardware-designs adder verilog-hdl verilog-project

Updated Sep 3, 2019
Verilog

sarthak268 / Embedded_Logic_and_Design

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This repository contains all labs done as a part of the Embedded Logic and Design course.

c arm vhdl embedded-systems verilog xilinx vivado logic-programming zedboard verilog-hdl xilinx-fpga logic-circuit xilinx-vivado embedded-c vhdl-code pmod xilinx-sdk verilog-programs verilog-project embedded-logic

Updated Jun 10, 2018

ashishrana160796 / VerilogTutorial

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Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

language tutorial practice vector embedded-systems verilog complex wire up-for-grabs circuit switches beginner-friendly logic-gates hdl verilog-hdl iverilog reg verilog-snippets verilog-programs verilog-project

Updated May 18, 2018
Verilog

TheSUPERCD / 8bit_MicroComputer_Verilog

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This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Feb 20, 2020
Verilog

ultraembedded / minispartan6-audio

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miniSpartan6+ (Spartan6) FPGA based MP3 Player

audio fpga verilog sd-card mp3player risc-v spartan6 rv32im verilog-project

Updated Sep 2, 2019
Verilog

mihir8181 / VerilogHDL-Codes

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Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

LutingWang / CPU_pipeplus

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BUAA Computer Organization Project7 CPU pipeplus

computer-architecture mips32cpu verilog-project

Updated Jan 19, 2019
Verilog

jiachen-meng / verilog-smart-park

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This is the final project of Digital Systems Fall 2019@ University of Toronto

verilog-project

Updated Jan 19, 2020
Verilog

LutingWang / CPU_pipeline

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BUAA Computer Organization Project5 CPU pipeline

computer-architecture mips32cpu verilog-project

Updated Jan 19, 2019
Verilog

pendkeomkar / SPI

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Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

verification verilog spi uvm verification-methodologies verilog-hdl verilog-programs verification-codes verilog-project verification-component

Updated Aug 21, 2018

LutingWang / CPU_monocycle

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BUAA Computer Organization Project4 CPU monocycle

computer-architecture logisim mips32cpu verilog-project

Updated Jan 19, 2019
Verilog

himanshu520 / MonoPong

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FPGA based single player game

fpga xilinx-fpga xilinx-vivado mono-pong-game verilog-project zybo-board

Updated Aug 31, 2018
Verilog

mateuspinto / FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

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Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

fpga verilog verilog-hdl fpga-firmware altera-fpga verilog-simulator verilog-project altera-de2