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verilog

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chisel3
crepererum
crepererum commented Jun 6, 2020

Type of issue: other enhancement

Impact: no functional change

Development Phase: request

Other information
This is more a meta-issue mostly related to the beginners user experience. I think most of these issues are not done by more experienced devs.

If the current behavior is a bug, please provide the steps to reproduce the problem:

  1. Start with [chisel-templat
verilator
wsnyder
wsnyder commented May 23, 2020

Internal code coverage shows the following DPI functions in verilated_dpi aren't covered at all. We should improve the tests to check them and validate against another simulator.

void* svGetArrElemPtr(const svOpenArrayHandle h, int indx1, ...) {
void svPutBitArrElem1VecVal(const svOpenArrayHandle d, const svBitVecVal* s, int indx1) {
void svPutBitArrElem2VecVal(const svOpenArrayHandle d,
litghost
litghost commented Mar 5, 2020

Proposed Behaviour

None of the core VPR algorithms should care if the relevant t_physical_tile is an input / output / IO type.

Current Behaviour

Some behavior is still dependent on whether a tile is an input / output / IO type.

Possible Solution

The relevant code shouldn't need to care. Once all callsites of is_input_type/is_output_type/is_io_type are removed, the

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

  • Updated Apr 24, 2020
  • Haskell

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