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Mar 22, 2020 - SystemVerilog
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fpga-soc
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NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn
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Dec 18, 2018
The Antikernel operating system project
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Apr 23, 2020 - Verilog
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Mar 10, 2020 - VHDL
Partial implementation of Knuth's MMIX processor (FPGA softcore)
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Feb 19, 2020 - C
jahofmann
commented
Nov 4, 2019
As part of the work in issue #79, the benchmarks that have been deprecated for a while have been removed as they were not functional anymore.
To evaluate the performance of TaPaSCo properly, again, there should be a replacement that checks the different performance critical parts of TaPaSCo.
There were four different tests:
- benchmark-alloc-free: Check memory allocation performance
- be
2
Open
LKM: man pages
Verilog Convolutional Neural Network on PYNQ
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Apr 2, 2018 - VHDL
Audio Signal Processing SoC
audio
linux
fpga
signal-processing
vhdl
university-project
ip
fpga-soc-linux
de1-soc
fpga-soc
embedded-linux
qsys
fpga-audio
hardware-software-design
hsd
fhhagenberg
terasic-de1-soc
audio-signal-proccesing
university-of-applied-science
asp-soc
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Mar 13, 2018 - VHDL
RFSoC Spectrum Analyser Module on PYNQ
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Apr 8, 2020 - Python
Basic RISC-V Test SoC
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Apr 7, 2019 - Verilog
DE10-Nano FPGA Configuration from Linux. Software to configure the FPGA portion of the Cyclone V SoC.
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Jun 4, 2019 - C
A SoC implementation of a PDP-8/I for the PiDP-8/I console
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Jun 7, 2020 - C
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
linux
fpga
python-script
intel
bootloader
altera
can-bus
fpga-soc
embedded-linux
quartus-prime
intel-fpga
altera-fpga
hps
fpga-configuration
soc-fpga
fpga-fabric
mapping-hps-peripherals
rsyocto
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Jun 30, 2020 - Verilog
terrillmoore
commented
Jul 21, 2019
We use a few rules for Verilog style, including:
- Standard header
- no use of tab characters (\t)
- no trailing whitespace
- normal indentation is 4 spaces
- naming conventions (use of _i and _o suffixes, negative logic notation, upper-case for macros)
We ought to write down the rules.
Audio Signal Processing SoC Project Website
audio
university-project
fpga-soc-linux
de1-soc
audio-signal-processing
fpga-soc
fgpa
fpga-audio
hardware-software-design
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Apr 6, 2017 - HTML
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to help with unit tests, be able to turn off the text on the patterns. This will provide known image for testing inputs, testing loopback, and testing outputs (like the encoder).
I can see a case for leaving some of it on, but I would prefer the option of having the same image across all everythings. The case for testing for text on an image doesn't seem worth the effort in providing a UI/A