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CarlFK
CarlFK commented Apr 17, 2018

to help with unit tests, be able to turn off the text on the patterns. This will provide known image for testing inputs, testing loopback, and testing outputs (like the encoder).

I can see a case for leaving some of it on, but I would prefer the option of having the same image across all everythings. The case for testing for text on an image doesn't seem worth the effort in providing a UI/A

jahofmann
jahofmann commented Nov 4, 2019

As part of the work in issue #79, the benchmarks that have been deprecated for a while have been removed as they were not functional anymore.

To evaluate the performance of TaPaSCo properly, again, there should be a replacement that checks the different performance critical parts of TaPaSCo.

There were four different tests:

  • benchmark-alloc-free: Check memory allocation performance
  • be
terrillmoore
terrillmoore commented Jul 21, 2019

We use a few rules for Verilog style, including:

  1. Standard header
  2. no use of tab characters (\t)
  3. no trailing whitespace
  4. normal indentation is 4 spaces
  5. naming conventions (use of _i and _o suffixes, negative logic notation, upper-case for macros)

We ought to write down the rules.

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