A compiler, assembler, and processor.

A neural branch predictor tested using CPU emulator, testing both supervised learning and reinforcement learning (for COS 583: Great Moments in Computing at Princeton University)

VHDL code of three branch predictors

Computer Architecture

Branch prediction using branch correlations. Made as part of the course Data-driven Program Analysis (CS686)

C++ Macro definitions for easy branch hinting.

Project done as a course-project for CS422 (Computer Architecture) at IIT Kanpur, in April-March 2015, under guidance of prof. Mainak Chaudhuri. Idea is to implement the popular perceptron based branch predictors for different memory limits and evaluate the performance on CBP-2014 kit. Also try to explain the performance result.

The WIOM: A RV32IM In-Order pipelined cpu with no cache and a naive branch predictor.

C++ based implementation of the VPC indirect branch prediction algorithm.

Fork of Seth's ChampSim repository

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.

Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4