risc-v

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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Aug 28, 2021 - Python
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Aug 29, 2021 - Scala
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Mar 24, 2021 - Verilog
About this question, here is a unified reply.
We need to see this place where one is the definition and load the configuration.
https://github.com/sipeed/MaixPy/blob/master/components/micropython/port/builtin_py/board.py
If you don't provide the configuration, you won't get the concrete variable.
If it is SIPEED published hardware, the appropriate configuration is provided here.
htt
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Aug 26, 2021 - C#
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Aug 29, 2021 - C
To help users identify how their Verilator simulation of Ibex was built it would be nice to display the parameters (or name of the configuration) that were chosen when running the simulation -- either by default, or as part of a config parameter (e.g. --version
).
The parameter values should be available from Verilator at runtime, so we probably don't need any compile-time magic to pass them i
I have just recently installed RARS as a replacement for RVS and there doesn't seem to be the ability to display the hex and decimal value at the same time.
If there is already a way to do this apologies for the issue.
Breakpoint weirdness
This is discussed a bit more in #456.
Currently, to copy off files from the fs is to 1. mount, 2. chattr, 3. chmod/chown, 4. copy files off. However, this is destructive to the fs (since it changes permissions/users). Instead, there should be a less invasive way to copy off files that doesn't mess with the underlying fs so that people can copy the fs and use it somewhere else.
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May 3, 2020 - Verilog
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Dec 11, 2020 - Forth
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Jul 19, 2021 - Verilog
set_mode_X()
HIL functions need to support returning an error if hardware does not support that mode or if the implementation cannot put the hardware in to that mode at that time. See for an example where panic is used instead of returning an error https://github.com/tock/tock/pull/2629/files.