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34 public repositories
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An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
QKeras: a quantization deep learning library for Tensorflow Keras
Updated
Jul 22, 2021
Python
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
Updated
Apr 22, 2019
Jupyter Notebook
Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
Updated
Jun 27, 2018
Objective-C
Small-scale Tensor Processing Unit built on an FPGA
Updated
Aug 4, 2019
Verilog
OpenCL based CNN Accelerator on Intel DE10 Nano FPGA.
Updated
Jun 8, 2021
Objective-C
OPAE porting to Xilinx FPGA devices.
Lenet for MNIST handwritten digit recognition using Vivado hls tool
Updated
Jul 22, 2020
Objective-C
This project implements a convolution kernel based on vivado HLS on zcu104
Hardware-accelerated sorting algorithm
Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
Co-processor for whole genome alignment
Updated
Jun 6, 2020
Verilog
A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer
Updated
Dec 11, 2018
Assembly
Visual System Integrator - Accelerate your embedded development
Updated
Jun 18, 2018
Python
TCP/IP and UDP/IP protocol stack off-loading
Updated
Aug 9, 2020
Verilog
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
Updated
May 20, 2020
Verilog
Updated
Oct 31, 2020
Verilog
Analysis and design methodology of convolutional neural networks mapping on reconfigurable logic
This repository contains detailed notes of all chapters and all three projects completed in Intel-Edge-AI NanoDegree.
Updated
Mar 12, 2021
Jupyter Notebook
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Convolutional accelerator kernel, target ASIC & FPGA
Updated
Jun 21, 2021
Verilog
Janus astrophysics Simulator implemented on ZU19EG Ultrascale+
Updated
Mar 12, 2018
LLVM
A FPGA Based Square Root Approximation Coprocessor
Updated
Jul 13, 2020
VHDL
Projekt zaliczeniowy w ramach przedmiotu "Systemy Cyfrowe". Projekt miał na celu stworzenie układu DSP do pomiaru odległości za pomocą odbitego światła lasera. Wykonano układ który można finalnie uruchomić na płytce Cyclone IV Altera (model EP4CE6E22), który można sterować bezpośrednio na płytce. Objaśnienie projektu znajduje się w załączonym do repozytorium raporcie
Updated
Jun 22, 2021
Stata
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
Updated
Mar 29, 2021
SystemVerilog
Janus Algorithm in C++ version without FPGA acceleration.
TURBOdeb #xohw19-157 #TuringBombe #Enigma
Undergraduate internship Dec. 2020 ~ Feb. 2021
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