verilog

See discussion in chipsalliance/chisel3#2124 (comment)

[...] since the increase to 64-bit wide busses, using drop-down lists to choose the bit width and selecting bits is tedious, [...]

By @maehne in #617 (comment)

Thanks for taking the time to report this.

What would you like added/supported?

// File: dly_warning.sv

// verilator lint_off ASSIGNDLY

module dly_warning (
    input logic a_in,
    input logic [2:0] delaycw,

    output logic a_out
);

timeunit 1ns;
timeprecision 1ns;

time dly;

assign dly = 5 * delaycw;
assign #dly a_out = a_in;     // Warning ASS

Several users have asked for an example of how to use the makefiles in projects that contain precompiled and/or encrypted IP cores or libraries. There should be a simple example. It will likely not work for them, but could act as a template.

Alternatively, documentation or an explicit API for these objects would also help.

Tuo Xie requested the ability to visualize clocking (pins & wires I believe). We should make it easier to visualize subsets of the device routing resource and types of routing nets.

Proposed Behaviour

Add filtering to the rr_nodes displayed (ToggleRR), and to the nets displayed (ToggleNets). I think we should have an option to filter what is shown by node type, node name (segment or pin t