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computer-architecture
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Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr
and instruction operating with CSRs:
riscv-software-src/riscv-tests#258
riscv-software-src/riscv-tests#263
Your obj
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The destructor hangs at pipe.stop()
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Currently, things such as the program loaded into the editor and the active processor are stored as settings and persisted between program invocations.
We should be able to add more features like this, to persist things such as: