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Dec 24, 2021 - Python
verilog
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I observed in Logisim-Evolution 3.7.1 that once the zoom factor for the gui is set manually, there is no possibility to set it back to auto. Maybe a reset button in the preferences window could be inserted.
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Mar 24, 2021 - Verilog
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Dec 12, 2021 - C
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Dec 28, 2021 - Haskell
Thanks for taking the time to report this.
What would you like added/supported?
// File: dly_warning.sv
// verilator lint_off ASSIGNDLY
module dly_warning (
input logic a_in,
input logic [2:0] delaycw,
output logic a_out
);
timeunit 1ns;
timeprecision 1ns;
time dly;
assign dly = 5 * delaycw;
assign #dly a_out = a_in; // Warning ASS
Several users have asked for an example of how to use the makefiles in projects that contain precompiled and/or encrypted IP cores or libraries. There should be a simple example. It will likely not work for them, but could act as a template.
Alternatively, documentation or an explicit API for these objects would also help.
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Dec 23, 2021 - Verilog
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Dec 27, 2021 - JavaScript
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Nov 26, 2021 - Verilog
Tuo Xie requested the ability to visualize clocking (pins & wires I believe). We should make it easier to visualize subsets of the device routing resource and types of routing nets.
Proposed Behaviour
Add filtering to the rr_nodes displayed (ToggleRR), and to the nets displayed (ToggleNets). I think we should have an option to filter what is shown by node type, node name (segment or pin t
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Nov 17, 2021
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Dec 28, 2021 - Verilog
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Sep 18, 2021 - Verilog
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Type of issue: other enhancement