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xilinx

Here are 476 public repositories matching this topic...

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

linux fpga zynq hls hardware wifi verilog xilinx sdr analog-devices ieee80211 xilinx-fpga dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Updated Apr 19, 2022
C

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated Apr 17, 2022

hdl-util / hdmi

Open

Translate README.md

sameer commented May 16, 2020

If you speak another language, I would appreciate your help in translating the README.md.

For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.

^ I've tried to do this a bit in the French README. The only thing you need to replicate when

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help wanted good first issue

Xilinx / brevitas

Brevitas: quantization-aware training in PyTorch

text-to-speech fpga pytorch speech-recognition neural-networks image-classification xilinx quantization hardware-acceleration brevitas

Updated Apr 15, 2022
Python

prjxray

f4pga / prjxray

Open

Assign xc7 prefix to prjxray tools to avoid conflicts

4

acomodi commented May 25, 2020

All the tools in prjxray should have an xc7 prefix, so to make them unique.

E.g. bitread or bittool could enter in conflicts with other tools names.

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good first issue

Open

Document remaining bits in opentitan bitstream

3

Open

Refactor xjson library

Find more good first issues

pConst / basic_verilog

Must-have verilog systemverilog modules

spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver

Updated Apr 23, 2022
Verilog

trabucayre / openFPGALoader

Universal utility for programming FPGA

fpga intel cyclone xilinx lattice bitstream arty gowin trenz-gowin-littlebee

Updated Apr 23, 2022
C++

trivialmips / nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

Updated Jul 7, 2020
SystemVerilog

Cr4sh / s6_pcie_microblaze

PCI Express DIY hacking toolkit for Xilinx SP605

kernel fpga backdoor rootkit hypervisor uefi xilinx hyper-v dma microblaze pci-e

Updated May 26, 2021
C

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

python infrastructure asic fpga simulation vhdl verification xilinx synthesis regression-testing altera hardware-designs lattice hardware-libraries poc-library vlsi testbenches hardware-modules osvvm uvvm vunit

Updated Nov 29, 2020
VHDL

olofk / edalize

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

Updated Apr 14, 2022
Python

ultraembedded / biriscv

Sponsor

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Apr 5, 2022
Verilog

f32c / f32c

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

arduino fpga mips riscv xilinx altera lattice

Updated Apr 22, 2022
VHDL

Xilinx / SDAccel_Examples

SDAccel Examples

c aws fpga cpp opencl xilinx sdx sdaccel nimbix

Updated Jul 16, 2020
C++

bperez77 / xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

fpga driver xilinx zedboard axi-dma linux-driver axi-vdma dma-driver xilinx-axi-dma xilinx-axi-vdma userspace-dma fpga-dma

Updated Nov 6, 2021
C

ZipCPU / wb2axip

Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

Updated Apr 7, 2022
Verilog

Vitis_Accel_Examples

Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples

zynq xilinx soc alveo fpga-programming acap vitis

Updated Apr 19, 2022
Makefile

Xilinx / CHaiDNN

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

deep-neural-networks inference dnn xilinx alexnet googlenet embedded-vision xilinx-ultrascale-mpsocs

Updated Jul 9, 2019
C++

pavel-demin / red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Apr 1, 2022
C

eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

linux fpga boom xilinx vivado risc-v nexys-video vc707 rocketchip genesys2 kc705

Updated Apr 8, 2022
C

definelicht / hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga hpc xilinx sdaccel high-level-synthesis vivado-hls intel-fpga vitis intel-fpga-opencl

Updated Jan 21, 2022
C++

jofrfu / tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

linux iot fpga zynq tensorflow assembly vhdl embedded-systems internet-of-things hardware-architectures verilog xilinx vivado tensor hardware-designs hardware-acceleration fpga-accelerator hardware-description-language ip-core tpu

Updated Jan 5, 2019
VHDL

tymonx / logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado

fpga xilinx vivado rapidwright

Updated Apr 20, 2022
Java

lastweek / fpga_readings

Recipe for FPGA cooking

fpga hls rtl verilog xilinx vivado-hls

Updated Jul 14, 2021
Verilog

suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

python vim language-server vhdl issue-tracker standalone verilog xilinx syntax-checker systemverilog trademarks hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp

Updated Mar 3, 2022
Python

fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

tcp xilinx vitis network-kernel

Updated Nov 15, 2021
C++

Xtra-Computing / ThunderGP

Open

Accessing Properties of Vertices with Null Out-Degree

10

pf-un commented Mar 22, 2021

Hi everyone.

I'm wondering about accessing the property of vertices with out-degree equal to 0.
I understand these are somehow filtered out of certain computations since they generate no updates, but they should still receive updates so I'd like to access their property after some number of supersteps.

I would also appreciate an explanation on the various MEM_ID pointers.

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good first issue

z4yx / petalinux-docker

Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)

docker xilinx petalinux

Updated Feb 2, 2022
Dockerfile

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