yosys

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Here are 88 public repositories matching this topic...

amaranth-lang / amaranth

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A modern hardware definition language and toolchain based on Python

fpga hdl yosys amaranth-hdl

Updated Sep 20, 2022
Python

cariboulabs / cariboulite

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CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

radio rpi fpga pi software sdr raspberry icestorm rf yosys ice40 defined

Updated Aug 11, 2022
C

The-OpenROAD-Project / OpenLane

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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Sep 22, 2022
Verilog

m-labs / nmigen

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A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga hdl yosys nmigen

Updated Jan 8, 2022
Python

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Sep 20, 2022
Python

nturley / netlistsvg

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draws an SVG schematic from a JSON netlist

visualization diagram elk yosys klayjs netlist

Updated Apr 22, 2022
JavaScript

zachjs / sv2v

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SystemVerilog to Verilog conversion

conversion verilog systemverilog yosys

Updated Jul 24, 2022
Haskell

efabless / caravel_mpw-one

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Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad openram sky130

Updated Feb 22, 2022
Verilog

forflo / yodl

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A VHDL frontend for Yosys

vhdl yosys

Updated Feb 27, 2017
C++

efabless / caravel

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Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad vexriscv openram sky130

Updated Sep 21, 2022
Verilog

scarv / xcrypto

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XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Mar 31, 2021
Verilog

dadamachines / doppler

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Arduino compatible – Cortex M4F & FPGA Development Board

arduino fpga icestorm yosys ice40 ice40up5k samd51

Updated Mar 22, 2019

ECP5-PCIe / ECP5-PCIe

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Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

fpga trellis yosys pcie ecp5 nextpnr prjtrellis gateware pcie-interface amaranth

Updated Jun 27, 2022
Python

chipsalliance / fpga-tool-perf

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FPGA tool performance profiling

toolchain fpga perf performance-analysis yosys conda-environment vpr arachne-pnr nextpnr symbiflow f4pga

Updated Sep 22, 2022
Python

mattvenn / fpga-sdft

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sliding DFT for FPGA, targetting Lattice ICE40 1k

fpga verilog fourier fft icestorm yosys sdft

Updated Apr 24, 2020
Verilog

chipsalliance / yosys-f4pga-plugins

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Plugins for Yosys developed as part of the F4PGA project.

toolchain fpga eda xilinx yosys xilinx-fpga yosys-plugin f4pga

Updated Sep 13, 2022
Verilog

tmeissner / psl_with_ghdl

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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Aug 15, 2022
VHDL

PyFPGA / pyfpga

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A Python package to use FPGA development tools programmatically.

Updated May 27, 2022
Python

SymbiFlow / sphinxcontrib-hdl-diagrams

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Sphinx Extension which generates various types of diagrams from Verilog code.

documentation fpga sphinx documentation-tool rtl verilog diagrams hdl yosys sphinx-extension symbiflow

Updated Dec 7, 2021
Python

ghdl / docker

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Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Jul 27, 2022
Shell

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