risc-v

目前 RT-Thread 仓库为了保证代码的正确性，基本每个PR都会编译一遍所有的bsp，其中环境安装是最耗时的部分。如果可以利用 github 的cache机制，就可以极大的加快仓库ci的执行效率。

参考

• https://mrseawave.github.io/blogs/articles/2021/12/17/github-actions-cache/
• https://docs.github.com/en/enterprise-cloud@latest/rest/actions/cache

• The set_mode_X() HIL functions need to support returning an error if hardware does not support that mode or if the implementation cannot put the hardware in to that mode at that time. See for an example where panic is used instead of returning an error https://github.com/tock/tock/pull/2629/files.

For those who want the fastest possible simulation, and do not care about any form of datapath visualization, there should be an option to select an ISA simulator processor model.

This processor model, while complying with the ProcessorInterface, will in VSRTL be implemented as a "black box" - in other words, pure C++ logic.

To help users identify how their Verilator simulation of Ibex was built it would be nice to display the parameters (or name of the configuration) that were chosen when running the simulation -- either by default, or as part of a config parameter (e.g. --version).

The parameter values should be available from Verilator at runtime, so we probably don't need any compile-time magic to pass them i

I have just recently installed RARS as a replacement for RVS and there doesn't seem to be the ability to display the hex and decimal value at the same time.

If there is already a way to do this apologies for the issue.

attached is a screenshot of how RVS handles it

This is discussed a bit more in #456.

Currently, to copy off files from the fs is to 1. mount, 2. chattr, 3. chmod/chown, 4. copy files off. However, this is destructive to the fs (since it changes permissions/users). Instead, there should be a less invasive way to copy off files that doesn't mess with the underlying fs so that people can copy the fs and use it somewhere else.