uart-verilog

This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

fpga verilog altera buzzer uart-verilog verilog-hdl 7-segment ir-receiver quartus-prime logifind nec-verilog cyclone-iv ep4ce6e22c8n pl2303 easyfpga

Updated Sep 10, 2019
Verilog

GLADICOS / UART

Star

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

uart icarus-verilog systemc gtkwave systemc-model uart-verilog dut

Updated Oct 29, 2020
Verilog

kishanpatelec / UART-for-bluetooth-module

Star

bluetooth uart uart-verilog uart-protocol hc-05 uart-controller uart-tx uart-com uart-receiver

Updated Mar 16, 2019
Verilog

ColtonBeery / UART_TX

Star

Basys 3 UART Tx for COMPE470L class

verilog uart-verilog uart-tx basys3-fpga

Updated Mar 17, 2019
Verilog

TheLeopardsH / UART

Star

Universal Asynchronous Receiver Transmitter

fpga verilog uart uart-verilog uart-receiver receiver-transmitter

Updated Aug 11, 2020
Verilog

mwbryant / uart-CI

Sponsor

Star

Basic continous integration testing for verilog projects

fpga verilog uart uart-verilog verilator uart-tx

Updated May 22, 2020
C++

STjurny / BasicUART

Star

Small light-weight implementation of UART in Verilog.

fpga verilog uart serialport uart-verilog ice40 tinyfpga alchitry

Updated Dec 20, 2020
Verilog

BrunoBMoura / BM_CORE

Star

Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.

mips architecture operating-system uart uart-verilog risc-processor

Updated Jul 25, 2019
Verilog

Shubhayu-Das / VL504-project

Star

Displaying images taken from an OV7670/laptop camera

uart-verilog vga basys3 ov7670

Updated Dec 30, 2021
Python

mengstr / vuart

Star

WIP - Smallish UART written in Verilog

verilog uart uart-verilog wip-do-not-use

Updated Feb 6, 2020
Verilog

KevinWang96 / UART_Verilog_Based

Star

Verilog Modeling of UART Tx and Rx

uart-verilog verilog-hdl uart-protocol

Updated May 5, 2020
Verilog

sidhantp1906 / UART

Star

UART implementation using Verilog HDL

rtl verilog uart-verilog xilinx-fpga uart-protocol xilinx-ise

Updated Jan 23, 2022
Verilog

PhatLe15 / Computer-Architecture-Design

Star

Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.

performance-analysis uart-verilog soc truth-tables mips-processor fpga-validation